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Lockstepping Multiple PowerPC Processors

Q: We are interested in running two PowerPC processors in lock-step. Will

they do that?

We are able to test these parts on a cycle-by-cycle tester because they are deterministic and

therefore should work in lockstep (given proper initialization which the tester requires also).

Initialization should include the following steps:

On the 603 and 603e all scanable registers are initialized during reset (asserting both H-reset and

T-reset pins). The array structures (FPRs, GPRs,caches, segment-registers, BATs, TLBs and

BIU-data queues) are not initialized. (There are also three latches in the JTAG/COP/PLL that are

not initialized but they are irrelevent to this discussion.)

On the 604e, one has to initialize the Branch History Table (BHT), or keep it disabled, and clear the BTAC.

Upon Reset the hardware also performs the following:

- Translation is disabled (All)

- The Icache and Dcache are disabled (All)

- All Dcache dirty bits are cleared (603e, 740/750)

- All Dcache and Icache valid bits are cleared (603e, 740/750)

- All Dcache and Icache LRU bits are initialized (603e, 740/750)

- The BHT is disabled (604,604e,740/750).

- The BTAC is disabled (604, 604e).

- The BTIC is disabled (740/750). <- is this true

If the following are performed as part of the reset sequence

execution should remain deterministic and in lock_step.

- Initialize all of the GPRs

- Initialize all of the FPRs

- Initialize all of the Segment Registers

- Invalidate all of the TLB entries

- Initialize all of the BAT registers

- Initialize the BHT before enabling (604, 604e, 740/750) <- How?

- Invalidate the BTIC before enabling (740/750) <- How?

- Invalidate the ICACHE and DCACHE via the HID0 register (604e) <- Is this

the equivalent of the 603e initializing the valid and LRU bits?

- Flush the BTAC by disabling and re-enabling using two successive mtspr

instructions (604e)

Note: The BAT arrays has one caveat. The arrays are strobed regardless of whether translation is enabled.

If multiple hits occur then the cooresponding BPRN ﬁelds are corrupted.

Therefore, at reset initialize all of the BATs to zero by writing the Upper-BAT registers ﬁrst then the

Lower-BAT registers. (this assures that random data in the BATs does not cause multiple hit with new data

being written). Also, when changing BAT registers the programmer must assure that there are no multiple

hits (during and after the change).