FAQ17.pdf

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Correlation between 60x address bus and 106R4/SDMA signals
for 64-Mbit devices
Q: Figure 6-23 on page 6-41 of the 106 UM shows SDRAM address multiplexing for the
106 Rev 3.0 (16 Mbit devices), but the 106 Rev 4.0 Supplement does not show
memory address muxing for 64-Mbit devices. What is the correlation between 60x
address bus and SDMA signals for 64-Mbit devices for 106 Rev 4.0?
A:
Figure 6-23 is incorrect. The following describes the address
muxing for all SDRAM devices:
SDMA and SDBA are labeled as in the MPC106 Rev 4.0 supplement Table
1, ÒMPC106
Rev.4.0 SDRAM Interface SignalChanges (that is,
SDBA0 = U16
SDBA1/SDMA0 = N15
SDMA1 = P1
SDMA2 = T16
SDMA3 = R16
SDMA4 = P15
SDMA5 = P16
SDMA6 = N16
SDMA7 = M15
SDMA8 = M16
SDMA9 = L15
SDMA10 = K15
SDMA11 = K16
SDMA12 = J16
2 bank 16 Mbit SDRAM
Physical addr
A0-4 A5 A6 A7 A8 A9 A10-20 A21-28 A29-31
|_____|__|______|______|
|
|
|
|
|
|
|
\
|
|
\
col addr; SDMA[5-12]
|
\
row addr; SDMA[2-12]
\
row bnk; SDBA0
col addr; SDMA[3-4]
2 bank 64 Mbit SDRAM
Physical addr
A0-4 A5 A6 A7 A8 A9 A10-20 A21-28 A29-31
|_____|__|__|__|______|______|
|
| | |
|
|
|
| | |
|
\
|
| | |
\
col addr; SDMA[5-12]
|
| | \
row addr; SDMA[2-12]
|
| \
row bnk; SDBA0
|
\
row addr; SDMA0
\
row addr; SDMA1
col addr; SDMA[3-4]
4 bank 64 Mbit SDRAM
Physical addr
A0-4 A5 A6 A7 A8 A9 A10-20 A21-28 A29-31
|_____|__|__|__|______|______|
|
| | |
|
|
|
| | |
|
\
|
| | |
\
col addr; SDMA[5-12]
|
| | \
row addr; SDMA[2-12]
|
| \
row bnk; SDBA0
|
\
row bnk; SDBA1
\
row addr; SDMA1
col addr; SDMA[3-4]

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