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RCSn_ signal timing

Figure 6-41 in the 106 UM shows Flash Write Timing. From that diagram, I see

that WE_ signal timing is controlled by ROMNAL. What controls RCSn_ signal

timing?

We use what some Flash manufacturers call Chip Select Controlled Write.

ROMFAL controls the interval that WE_ stays asserted, and ROMNAL controls the

minimum interval between assertions of WE_ during Flash writes.

During Flash writes, RCSn_ is always asserted one clock before WE_ and remains

asserted until one clock before WE_ is negated. Effectively, ROMFAL and

ROMNAL control RCSn_ timing during Flash writes.