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Multiple TEAs

Due to the pipelining available on MPC60X devices how do you handle TEA's or multiple

TEA's?

If machine check, MSR bit 19 - ME, is enabled in the PowerPC MSR register a TEA on a

MPC60X transaction will result in the processor taking a machine check exception. Different

implementations of the PowerPC Microprocessor Family handle this asynchronous/nonmaskable

interrupt differently.

On MPC603,603e,603ev and 740/750

Multiple TEA's on data fetches will be seen by the device as a single TEA. If multiple data side

transactions(ie. loads and stores) are queued up and they all happen to access an illegal memory

range, after the ﬁrst TEA is returned the MPC device will continue clearing it's data side queue

and ignore subsequent TEA's on those transactions. After it is ﬁnished ﬂushing the data queues it

will commence fetching of the machine check exception handler at address 0xXXX00200 (based

on the MSR-IP bit setting). All of these transactions (which are sent to the bus and begun by the

MPC device) must be responded to by the memory controller. On the instruction side things are a

little different. If the instruction fetch stream ﬁnds itself in illegal memory and the memory con-

troller begins responding with TEA's then it is possible that the ﬁrst TEA will clear the ME bit in

the MSR register (as part of exception processing) and a consecutive prefetch, which is TEA'ed,

will cause the processor to enter the checkstop state.

On MPC604,604e,Mach5

Multiple TEA's on data fetches can cause the processor to lock up. Upon seeing the ﬁrst TEA

returned to the processor it will clear the ME bit in the MSR (as part of it's exception processing)

before allowing the store queue and BIU to go idle. This results in a machine check if 1. ) consec-

utive stores are being issued(store queue not allowed to empty) or 2.) a load miss resulting in a

replacement copyback, if both of these transactions are TEA'ed (BIU not allowed to go idle). On

these devices, however, consecutive instruction fetches to illegal memory will not cause the

device to take a machine check since the next instruction fetch is not begun after the ﬁrst is

TEA'ed. Further more, starting with revision 3 of the MPC604 and Mach5 there is a mode which

can be entered by executing a privileged opcode on the JTAG/COP interface which allows the

store queue to empty and the BIU to go idle before the TEA is recognized.. For more information

contact the RISC Applications group.