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Interrupt Controllers for PowerPC CPUs

What is required to connect my interrupt signals to the PowerPC?

There are several ways to connect interrupts signals. If the interrupts are level-sensitive,

the interrupts can be merged with a single gate, or even connected together (“wired-or”)

if the signals are open-drain (as with PCI interrupt).

INTA

INTB

INTC

INTD

INT

Upon receiving an interrupt, the CPU must poll all possible interrupts sources to deter-

mine which device caused the interrupt. Prioritizing interrupts, as is typical with the

RISC philosophy, is not provided with hardware.

If the interrupts are edge-sensitive (such as ISA bus interrupts), then an external latch is

required to preserve the interrupt source. This latch must be readable at an location in

the memory map, and the hardware must also provide a means of clearing the latched

interrupt bit. Additional hardware, such as the ability to mask interrupts and to clear

individual bits in the latch interrupt status register are often desirable and make software

handling easier, but are not strictly required. At a minimum, the interrupt decoder

resembles the following diagram:

‘1’

INT3

CLR

INT

Clear Interrupt 3

Buffer

Read Interrupt Status

D(0:7)

This logic is typically present in a programmable interrupt controller (PIC) such as

implemented in various third-party chips. The industry standard 8259 PIC is available

from several manufacturers and also as a “megacell” (or macro) from many FPGA ven-

dors.