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Clock-to-Clock Skew

The PowerPC-compatible clock generators such as the MPC980 only guarantee

500

ps output-to-output skew. What effect will this have on my design?

The output-to-output skew causes uncertainty in the timing relationships between two

chips that must communicate, typically the PowerPC CPU and the MPC106. Output-to-

output skew is a static timing design that must be included in the timing analysis of any

high-speed design.

A detailed example of this is shown in application note AN1xxx, “SDRAM System

Design using the MPC106”. Consider the following timing values at 83 MHz:

Measurement

Bus Period

Clk-to-Output-Valid

Signal Propagation (Time of Flight)

Clock Skew

Clock Jitter

Input-Setup

Margin

Bus Speed Units

12.0

-7

-2.0

-0.5

-0.3

-1.0

1.2

Applying all the timing errors we see there is still 1.2ns of margin, so the system should

operate reliably even in the face of such clock uncertainty.