L811-824.pdf

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Advance Information
TECHNICAL
BULLETIN
Converting DSP56L811-Based Designs to the DSP56824
October 1, 1998
MOTOROLA, INC.
6501 William Cannon Dr. West
Austin, Texas 78735
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
©1998 MOTOROLA, INC.
DSP56L811/DSP56824
CONTENTS
CONTENTS
PURPOSE OF THIS DOCUMENT .............................................................................................................. 3
ARCHITECTURE OVERVIEW .................................................................................................................... 3
DESIGN CONVERSION OVERVIEW.......................................................................................................... 5
CONVERSION METHODOLOGY ............................................................................................................... 6
MODE 0 P MEMORY MAPS ....................................................................................................................... 6
MODE 1 P MEMORY MAPS ....................................................................................................................... 7
MODE 2 P MEMORY MAPS ....................................................................................................................... 8
X MEMORY MAPS ..................................................................................................................................... 9
SSI CHANGES ............................................................................................................................................ 9
OnCE FIFO AND 2ND BREAKPOINT ....................................................................................................... 10
VCO CURVE SELECT BIT ........................................................................................................................ 10
IRQ POSITIVE EDGE TRIGGER .............................................................................................................. 10
SZ BIT ADDED TO OMR ........................................................................................................................... 11
CORE INSTRUCTION DIFFERENCES..................................................................................................... 11
XCOLF SPECIFICATION CHANGED ....................................................................................................... 11
TRST/ RESET ASSERTION ...................................................................................................................... 12
PERIPHERAL CHANGES ......................................................................................................................... 12
DEBUG INSTRUCTION DIFFERENCES .................................................................................................. 12
56800 DEVELOPMENT TOOLS................................................................................................................ 13
CONTACTS ............................................................................................................................................... 13
APPENDIX A ............................................................................................................................................. 13
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Converting DSP56L811-Based Designs to the DSP56824
MOTOROLA
DSP56L811/DSP56824
PURPOSE OF THIS DOCUMENT
PURPOSE OF THIS DOCUMENT
This document details the differences between the DSP56L811 and DSP56824 that need to be
taken into consideration when redesigning a system based on the DSP56L811 to use the
DSP56824. The differences fall into two major categories: changes which must be addressed by
the user and enhancements which the designer may elect to implement.
Please refer to the DSP56L811 and DSP56824 Technical Data Sheets and their associated
documentation for complete information. A list of all associated documents is contained in
Appendix A.
Table 1: ARCHITECTURE OVERVIEW
DSP56L811
1K Program RAM
2K Data RAM
Three 16- Bit Timers
Real- time Timer, COP Timer
Two 8- bit Serial Ports (SPI)
Synchronous Serial Interface (SSI)
32 General Purpose I/ O Pins
Interrupt Capability on 8 GPIO
JTAG/ OnCEª Port for Debug
100 pin TQFP Package
DSP56824
32K Program ROM+ 128 Program RAM
3.5K Data RAM+ 2K Data ROM
Three 16- Bit Timers
Real- time Timer, COP Timer
Two 8- bit Serial Ports (SPI)
Synchronous Serial Interface (SSI)
32 General Purpose I/ O Pins
Interrupt Capability on 8 GPIO
JTAG/ OnCEª Port for Debug
100 pin TQFP Package
MOTOROLA
Converting DSP56L811-Based Designs to the DSP56824
3
DSP56L811/DSP56824
PURPOSE OF THIS DOCUMENT
16 to 32 GPIO lines
4
8
Program-
mable
Interrupt
GPIO
8
4
Serial
Periph.
Interface
(SPI0) or
GPIO
Serial
Periph.
Interface
(SPI1) or
GPIO
4
6
Synch.
Serial
Interface
(SSI) or
GPIO
2
Timer/
Event
Counters
or GPIO
Program Memory
1024
´
16 RAM
64
´
16 ROM
(boot)
Data
Memory
2048
´
16
RAM
PLL
GPIO
On-Chip
Expansion
Area
Clock
Gen.
16-bit
56800 DSP
Core
PAB
Address
Generation
Unit
XAB1
XAB2
XDB2
External
Address
Bus
Switch
Address
16
PGDB
Bus and Bit
Manipulation
Unit
PDB
CGDB
External
Data
Bus
Switch
Data
16
JTAG/
OnCEÔ
Port
Program Controller
Data ALU
16 x 16 + 36 Ñ> 36-bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Control
Bus
Control
4
5
3
Figure 1
56L811 BLOCK DIAGRAM
4
Converting DSP56L811-Based Designs to the DSP56824
MOTOROLA
DSP56L811/DSP56824
DESIGN CONVERSION OVERVIEW
16 to 32 GPIO lines
4
8
8
4
4
6
2
Data
Memory
3584
´
16 RAM
Data
Memory
2048
´
16 ROM
Serial
Synch.
Serial
Program
Timer/
Program-
Periph. Periph.
Serial
Memory
COP/
Event
mable
PLL Interrupt GPIO Interface Interface Interface Counters RTI 32 K
´
16 ROM
(SPI0)
(SSI) or or GPIO
(SPI1)
128
´
16 RAM
GPIO
or GPIO or GPIO
GPIO
PAB
Clock
Gen.
16-bit
DSP56800
Core
Address
Generation
Unit
XAB1
XAB2
External
Address
Bus
Switch
XDB2
External
Data
Bus
Switch
Address
16
PGDB
Bit
Manipulation
Unit
PDB
CGDB
Data
16
Control
JTAG/
OnCEª
Port
Program Controller
Data ALU
16
´
16 + 36
®
36-bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bus
Control
4
5
MODA/IRQA
MODB/IRQB
RESET
AA1445
Figure 2
56824 BLOCK DIAGRAM
DESIGN CONVERSION OVERVIEW
¥
¥
¥
The 56824 is pinout compatible with the 56L811; external hardware changes are required
in certain cases.
Code written for the 56824 is backward compatible to the 56L811 (except VCSO bit in
PCR1).
¥ Code that takes advantage of new 56824 features will not be backward compatible (e. g.
70MHz PLL wonÕt work on 56L811)
MOTOROLA
Converting DSP56L811-Based Designs to the DSP56824
5

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