MC68008_minimum_configuration_system.pdf

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frlOTOROLA
Sem
Ail897
Application Note
iconductor
Producfs
lnc.
\-,'
TIC68OO8
MIilIMUM
GOilFIGURATIOI{
SYSTEM
Prepared by
Geoffrey
Brown
and
Kyle
Harper
Advanced Microcomputer Applications
Engineering
M
icroprocessor
Division
Motorola
lnc.
Austin,
Texas
INTRODUCTION
This application
note
demonstrates
the
design
of
a
simple
high-performance MC68008
system
that
uses
the
MC6868l
Dual
Universal
Asynchronous Receiver
Transmitter
\-,
(DUART)
to interface
with
external devices. The MC68008
is
an
excellent
low-cost alternative
to
the
MC68000
and
features
an 8-bit
data bus
while maintaining
software
com-
patibility
with
the
rest
of
the
M68000
Family.
The MC6868l
DUART is
an
M68000
Family
data communications
chip
that
features:
Two
independent asynchronous serial
channels,
A
programmable
lGbit
counter/timer,
A
6-bit
parallel
input port,
and
An
8-bit
parallel
output port.
Emphasis
in
this
design concept
is
placed
upon performance,
expandability,
and
low chip
count.
The
M68000 system design
principles demonstrated
in
this
application
note include:
Interrupt
hardware,
Peripheral interfacing,
Memory
interface
techniques,
Memory
refresh
arbitration
in
an M68000
system, and
Efficient
serial
I/O
software.
The
system, described
in
this
design
concept, features
the
following
hardware:
(AS) by the
processor
and
are
terminated by the
assertion
of
data transfer
acknowledge
tDTffil
by
the peripheral or
memory
device
being
addressed.
Figures
l-4
show
the
minimum
hardware
necessary
for
an
MC68008
system
con-
sisting
of:
Address
decode
logic,
DmG
generation logic,
Reset
logic,
Bus
error
generation logic,
System
memory,
Interrupt
handling
logic,
and
An
MC6868l
interface.
The
following
paragraphs
detail
the
required hardware
as
ap-
plied to
the design concept described
in this application note.
Address Decode Logic
The
only tricky part
of
address
decoding
for
an
MC68008
system
is
that the
system
ROM
must be mapped
to
address
$00000
at reset.
It
would
be
impractical
to fix
the
ROM
at
the
bottom
of
the
address
ffi&p,
as
this would
not
allow for
dynamic
programming
of
interrupt
vectors.
To
provide
dynamic mapping
of
these
interrupt
vectors, an SN74LSI64
shift
register (U28)
is used
to
generate a
signal,
illAF,
which
is low
for
the
first
eight
memory
cycles
after
reset
(the
number
of
cycles necessary
to
fetch
the
reset
vector
and stack
pointer).
U28
is reset
along
with
the processor and is
clocked
by the rising
edge
of AT.
The
MAF
signal generated
by
U28
is used
by
the address decoding
circuitry to
force
selection
of
ROM
when
N[7rp
is
low
and
to
allow
normal
memory
decoding when
NIIP
is high.
An
8
MHz
MC68008 microprocessor,
gK
l6K
bytes
of
ROM,
bytes
of
dynamic
RAM with
no wait
states, and
An
MC6868l
DUART..
The following
paragraphs
describe
the hardware required
high-performance, expandable,
low
chip
count
MC68008
system
followed by a
description
of
the
software
necessary
to
initialize
and drive the
MC6868l
DUART.
In
the
design
given
in
this
application
note,
address
for
a
\rr
HARDWARE
REQUIREMENTS
The
MC68008 has an asynchronous bus
structure
in
which
bus
cycles
are
initiated
by
the
assertion
of
address
strobe
decoding
is accomplished
by
a
PALI6L8
(U22). This
PAL
is
programmed
to
generate
eight
chip-select signals
from
ten
in-
put
signals.
The inputs
to
the
PAL
are
the
upper
eight
ad-
dress
lines
(Al2-A19),
IACK
(the
NAND
of
the
MC68008
function
code
lines,
FCO-FC2), and the
NIAF
signal. Four
of
the
PAl-generated
chip-select lines are used
in
this
design
to
locate
RAM
at
the address $00000,
ROM
at
$'4.0000,
and the
MC68681
at
$F0000.
The
four
remaining
chip-select lines are
available
for
future
system expansion.
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A4
A3
A2
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RS3
52
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CM6665-15
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u13
u14
u15,
U16
u18
u19
u20
MC6800818
S
N74LS
148
S
N74LS
138
MCM68766
MC68681
S
S
S
N7415393
NT4LSOO
N74LSO4
,
U34
u22
u21
PAL16L8A
S
u23
u24
u25
u26,
U27
u28
u29
N74LSO5
N74LSO8
S
N74S
1O
S
s
N74532
u30,
u31
u32,
U36
u33,
U35
u37
u38
u39
N74LS
164
MC3456
S
N74F74
DDU-4-5100
S
N74LS
175
S
K1114A,
8
MHz
OSC
M
C1488
L/
MC1489
FIGURE4
-
MC68681 DUART

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