5572_INDEX.pdf

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INDEX
A
act, 6–5
act Bit, 4–13
Verified act, 4–13
Activation, 4–6, 4–8, 4–29, 5–30, 6–1, 6–6, 8–12,
9–1, 9–2, 9–4, 9–6
BR11, 4–25
BR12, 4–26
Customer Enable, 4–8
NR1, 4–6
Activation Timer, 4–26
Activation, Deactivation
Activation, 4–8
NR2, 4–8
ANSI T1.601–1992, 1–2
Applications, 2–1, 6–6, F–1
LAN Server, F–5, F–6
NT1, F–2
Pair Gain Application, Central Office Terminal,
2–3
Pair Gain Application, Remote Terminal, 2–3
Repeater Applications, 6–6
Smart NT1, F–4
Typical ISDN Applications, 2–2
U–Terminal, F–3
D
D Channel, 4–7, 4–35, 5–20, 9–13, 10–15, 10–17,
10–19
D Channel Interrupt, 4–7
D Channel Port, 5–20
Select DCH Access, 4–25
dea, 6–5
dea Bit, 4–14
Verified dea, 4–14
Deactivation, 4–8, 6–1, 8–12
LT Deactivation, 6–5
NT Deactivation, 6–5
Superframe Update Disable, 4–8
Digital Loop Carrier Systems, 4–20
E
Echo Canceller, 4–27
BR13, 4–27
eoc, 4–20, 5–7, 7–2, 9–1, 9–2, 9–4
Automatic eoc Processor Mode (b7 = 0, b6 =
Don’t Care), 4–22
crc Corrupt, 4–20
eoc Control 1:0, 4–21
eoc Processor Functions, 4–22
eoc Trinal–Check Mode (b7, b6 = 1,0), 4–22
R6, 4–10
Return to Normal, 4–6
ETSI ETR 080, 1–2
Eye, D–1
Eye Data, 4–29, 10–31
B
Baud Clock, 4–29
Byte Register, 5–9
C
Clock Reference, 3–12
Command/Indicate Channel, 8–11
Configurations, 5–4
Crystal, 3–12, 3–13, B–2, C–2
Crystal Characterization, H–1, H–2
Crystal Oscillator and Phase Locked Loop (PLL)
Pins, 3–12
MOTOROLA
F
febe, 4–24, 9–11
BR4, 4–14
febe and nebe Bits, 7–3
Received febe, 4–13
FIFOs, 1–2, 5–30
Frame Sync to U–Interface Propagation Delays,
5–30
Index–1
MC145572
G
GCI, 8–1, 8–19
GCI Frame Structure, 8–3
I
IDL Interface, BR7, 4–17
IDL2, 5–15
GCI 2B+D Mode Superframe Alignment, 5–27
GCI 2B+D Operation, 5–19
IDL2 2B+D Data Alignment to U–Interface
Superframe, 5–27
Initial State of B1 and B2 Channels, 5–30
Long Frame Operation, 5–18
Short Frame Operation, 5–16
IDL2 Interface, NR5, 4–10
Initialization, 9–2, 9–4, 9–6
Interrupt Status Register, 4–9
Interrupts, 7–7
NR3, 4–9
NR4, 4–9
M4 Delta Mode, 4–24
M4 Dual Consecutive Modes, 4–23
M4 Every Mode, 4–24
M4 Subchannel and Data Transparency, 7–2
M4 Trinal Check Mode, 4–24
M5 and M6 Channels, 7–3
Maintenance Bits, 4–12, 6–5
BR0, 4–12
BR1, 4–12
BR2, 4–13
BR3, 4–13
R6, 4–10
Master, 5–20, 8–19
Master/Slave, 4–18
MC14LC5472, 5–2, 5–4
Mechanical Outline, 11–3, 11–4
Mode, 4–21
NT/LT Invert, 4–21
Monitor Channel, 8–6
N
nebe, 4–24, 9–11
BR5, 4–14
Computed nebe, 4–13
febe and nebe Bits, 7–3
Nibble Register, 4–5, 5–6
L
Line Interface, B–1, C–2, E–4
2B1Q Line Interface Pins, 3–12
Line Interface Circuit, E–1
Loopback, 4–28, 4–34, 5–30
BR14, 4–28
BR6, 4–15
IDL2–Loop 2B+D, 4–15
IDL2–Loop B1, 4–15
IDL2–Loop B2, 4–15
IDL2–Loop Transparent, 4–15
Loopback Control Bits, 4–16
U–Loop 2B+D, 4–15
U–Loop B1, 4–15
U–Loop B2, 4–15
U–Loop Transparent, 4–15
O
Overlay Register, BR10, 4–24
P
Package Information, 11–1, 11–2
Parallel Control Port, 5–4, 5–11, 10–27
Pin Configuration
OR7, 4–32
OR8, 4–33
OR9, 4–34
Pin Descriptions, 3–1
2B1Q Line Interface Pins, 3–12
Control/Status Interface Pins, 3–8
Crystal Oscillator and Phase Locked Loop (PLL)
Pins, 3–12
Mode Selection Pins, 3–5
Power Supply Pins, 3–4
Time Division Multiplex Data Interface Pins, 3–6
Power–Down, 4–5
MC145572
MOTOROLA
M
Maintenance, 4–12, 6–5, 7–1, 7–7, 9–1
BR9, 4–21
Embedded Operations Subchannel, 7–2
febe and nebe Bits, 7–3
M4, 4–12
M4 Control 1:0, 4–22
Index–2
R
Register Maps, 4–1, 4–2, 4–3
Reset, Power–Down
Absolute Power–Down, 4–6
NR0, 4–5
Power–Down Enable, 4–5
Reset, 4–5
Revision Number, 4–29
Superframe Detect, 4–14
T
Test, 4–20, H–1
BR8, 4–20
Timeslot Assigner, 4–30, 5–22, 9–8
OR0, 4–30
OR1, 4–30
OR2, 4–30
OR3, 4–31
OR4, 4–31
OR5, 4–31
OR6, 4–31
Timeslot Selection, 5–26
S
Serial Control Port, 5–4, 5–5, 10–30
Slave, 5–20, 8–19
Superframe, 4–11, 5–27, 8–19, 10–33
LT – NT, 4–11
NT – LT, 4–11
W
Warm Start, 4–8, 6–5
MOTOROLA
MC145572
Index–3
Index–4
MC145572
MOTOROLA

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