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Chip Errata

DSP56004 Digital Signal Processor

Mask: D43G

ERRATA

Errata Description

1. In EMI, SRAM Absolute addressing mode, when the number of memory wait

states is greater than zero (ESTM3-ESTM0 > 0), EINR=1 and ERTS=0, and when

triggering a new read memory access while a read access is currently being exe-

cuted (i.e. the pipeline feature is being used), the current access might produce a

wrong address, and thus reads a wrong data.

Workaround: Do not use the pipeline feature in the above conditions. A new trig-

ger should be given after completion of the previous access.

Applies

to Mask

D43G

Motorola, Digital Signal Processing Division

6501 William Cannon Drive West, Austin, Texas 78735-8598

pg. 1 /stl/3-13-95

1995, Motorola

Chip Errata

DSP56004 Digital Signal Processor

Mask: D43G

NOTES

1. An over-bar (i.e. xxxx) indicates an active-low signal.

2. The letters seen to the right of the errata tell which DSP56004 mask numbers apply.

3. Manuals and data sheets may also have errata that is documented on the appropriate errata sheet as

discovered.

-end-

DSP56004 Errata

1995, Motorola

pg. 2 /stl/3-13-95