MPC823ICAN.pdf

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CPM Interrupt Controller
CPM Interrupt Controller
12- 1
What is the CPIC?
Definition
The CPIC is the focal point for all interrupts associated with the CPM. It accepts and
prioritizes all the internal and external interrupts from all functional blocks associated
with the CPM.
Example
CPM
Port C[4:15]
Timer1
Timer2
Timer3
Timer4
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I2C
PIP
IDMA1
IDMA2
SDMA
RISC Timers
To SIU Interrupt Controller
CPIC
V
N
To EPPC
Bolded names are sub-block maskable interrupt sources.
CPIC Features
Important functions of the CPIC are:
• Asserts an interrupt to the SIU interrupt controller at a user programmable level.
• Generates a unique vector number for each interrupt source.
• Prioritizes the interrupts for which it is responsible.
- Highest priority interrupt source is programmable by the user.
- Programmable priority between SCCs.
- Two priority schemes for the SCCs.
CPM Interrupt Controller
12- 2
What is a Sub-Block Maskable Interrupt?
Definition
If an interrupt source is maskable within the particular sub-block of which it is a part, it
is referred to as sub-block maskable.
SMCEx
3
BRK
Example,
SMCx
4
-
5
6
7
RX
SMCMx
3
BRK
4
-
5
6
7
RX
BSY TX
BSY TX
SMCx Interrupt to CPIC
CPM Interrupt Controller
12- 3
Programming Model
CICR -
CPM Interrupt Configuration Register
0
1
2
3
4
5
6
7
8
9
SCdP
16
17
18
19
20
21
22
23
24
IEN
25
26
10
11
SCcP
27
-
28
12
13
SCbP
29
30
P. 814
14 15
SCaP
31
SPS
IRL0_IRL2
HP0_HP4
CIPR -
CPM Interrupt Pending Register
0
1
2
3
4
5
6
PC15
SCC1 SCC2 SCC3 SCC4
PC14
16
17
18
-
19
Timer
3
Timer
1
7
8
9
SDMA
10
11
12
-
13
P. 816
14 15
I2C
31
-
PC13 PC12
23
-
24
Timer
4
IDMA IDMA
1
2
Timer
R_TT
2
20
21
22
25
26
27
28
29
30
PC11 PC10
PC9 PC8 PC7
PC6 SPI
SMC1 SMC2
PC5 PC4
/PIP
CIMR -
CPM Interrupt Mask Register
0
1
2
3
4
5
6
7
8
9
SDMA
P. 816
10
11
12
-
13
14
15
I2C
31
-
PC15
SCC1 SCC2 SCC3 SCC4
PC14
Timer
PC13 PC12
1
16
17
18
-
19
Timer
3
IDMA IDMA
1
2
Timer
R_TT
2
20
21
22
23
-
24
Timer
4
25
26
27
28
SMC2
29
30
PC11 PC10
PC9 PC8 PC7
PC6 SPI
SMC1 /PIP
PC5 PC4
CISR -
CPM In-Service Register
0
1
2
3
4
5
6
Timer
1
P. 816
7
8
9
SDMA
10
11
12
-
13
14
15
I2C
31
-
PC15
SCC1 SCC2 SCC3 SCC4
PC14
16
17
18
-
19
Timer
3
PC13 PC12
23
-
24
Timer
4
IDMA IDMA
1
2
Timer
R_TT
2
20
21
22
25
26
27
28
29
30
PC11 PC10
PC9 PC8 PC7
PC6 SPI
SMC1 SMC2
PC5 PC4
/PIP
CIVR -
CPM Interrupt Vector Register
0
1
2
VN
3
4
5
6
7
8
9
10
0
11
12
13
14
P. 814
15
IACK
CPM Interrupt Controller
12- 4
How to Prioritize the SCCs (1 of 2)
Introduction
The SCCs must be prioritized relative to each other. The user controls the order of
priority in the CICR, fields SCdP, SCcP, SCbP, and SCaP.
Priority
Matrix
SCC
SCC1
SCC2
SCC3
SCC4
Code
00
01
10
11
Lowest
SCdP
SCcP
SCbP
Highest
Priority
SCaP
CICR
Example
Problem: Set the priority so that SCC1 is highest, SCC3 is second hightest, SCC2 second
lowest, and SCC4 the lowest.
Lowest
SCC
SCC1
SCC2
SCC3
SCC4
Code
00
01
10
11
11
=
=
=
=
0;
2;
1;
3;
01
10
SCdP
SCcP
SCbP
Highest
Priority
SCaP
00
CICR
pdpr->CICR.SCaP
pdpr->CICR.SCbP
pdpr->CICR.SCcP
pdpr->CICR.SCdP
Exercise
Set the priority so that SCC2 is the highest priority, SCC3 is second highest, SCC4 is the
second lowest, and SCC1 is the lowest.
pdpr->CICR.SCaP
pdpr->CICR.SCbP
pdpr->CICR.SCcP
pdpr->CICR.SCdP
=
=
=
=
_;
_;
_;
_;
Comment
SCaP, SCbP, SCcP, and SCdP should all have different numbers.
CPM Interrupt Controller
12- 5

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